Publication

        * denotes corresponding author.

2026

• [TRETS] Xinya Luan, Zhe Lin*, Kai Shi, Liyang Dou, Jianwang Zhai, Kang Zhao. “AIEAnalyzer: An Analytical Framework for Versal AI Engine Performance Analysis.” In ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2026.

• [DATE] Yingxin Zeng, Binghao Cheng, Jianwang Zhai, Kang Zhao, Zhe Lin*. “AutoShrink: Adaptive Search Space Shrinkage for Large-Scale Pareto Optimization of HLS Designs.” In Proc. of Design, Automation and Test in Europe Conference (DATE), 2026.

• [ICC] Lihe Liang, Xiao Yun, Kuangxun Huang, Zhe Lin*, Zhongfeng Wang*. “JIMI: A Hierarchical Partition-Refinement MIQP Framework for Jitter Minimization in PONs.” In Proc. of IEEE International Conference on Communications (ICC), 2026.

• [ASP-DAC] Zibo Hu, Zhe Lin*, Renjing Hou, Xingyu Qin, Jianwang Zhai, Kang Zhao*. “HLS-Timer: Fine-Grained Path-Level Timing Estimation for High-Level Synthesis.” In Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2026.

• [TCAD] Kai Shi, Zhe Lin, Xinya Luan, Jianwang Zhai, Kang Zhao. “FVSpGEMM: A Comprehensive Framework for Exploiting Versal ACAP in High-Performance SpGEMM Acceleration.” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.

2025

• [TCAD] Sen Yan, Kuangxun Huang, Kang Zhao, Zhe Lin*. “Accurate, Efficient and Scalable Power Modeling for FPGA HLS.” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

• [ICCAD] Zefan Lin, Zedong Peng, Mingzhe Gao, Jieru Zhao*, Zhe Lin*. “HIPPO: A Hierarchy-Preserving and Noise-Tolerant Pre-HLS Power Modeling Framework for FPGA.” In Proc. of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025.

• [ICPADS] Kuangxun Huang, Xiao Yun, Lihe Liang, Zhe Lin*. “DARE: Towards Maximized Bandwidth Utilization of Dynamic Bandwidth Allocation for Next-Generation Passive Optical Networks.” In Proc. of International Conference on Parallel and Distributed Systems (ICPADS), 2025.

• [FPT] Liyang Dou, Zhe Lin*, Kai Shi, Xinya Luan, Kang Zhao*. “An End-to-End Tool Flow with Intrinsic-Level Kernel Optimization on Versal ACAP.” In Proc. of International Conference on Field Programmable Technology (FPT), 2025.

• [DAC] Xinya Luan, Zhe Lin*, Kai Shi, Jianwang Zhai and Kang Zhao*. “HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design.” In Proc. of ACM/IEEE 62nd Design Automation Conference (DAC), 2025.

• [DAC] Kai Shi, Zhe Lin*, Xinya Luan, Jianwang Zhai and Kang Zhao*. “VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration.” In Proc. of ACM/IEEE 62nd Design Automation Conference (DAC), 2025.

• [DAC] Jiawei Liang, Linfeng Du, Xiaofeng Zhou, Zhe Lin, Jiang Xu and Wei Zhang. “AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs.” In Proc. of ACM/IEEE 62nd Design Automation Conference (DAC), 2025.

• [FPGA] Enlai Li, Zhe Lin, Sharad Sinha and Wei Zhang. “TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms.” In Proc. of International Symposium on Field-Programmable Gate Arrays (FPGA), 2025.

2024

• [ICCD] Mingzhe Gao, Jieru Zhao*, Zhe Lin*, Wenchao Ding, Xiaofeng Hou, Yu Feng, Chao Li, Minyi Guo. “AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs.” In Proc. of IEEE International Conference on Computer Design (ICCD), 2024. Best Paper Award Nomination

• [DATE] Mingzhe Gao, Jieru Zhao*, Zhe Lin*, Minyi Guo. “Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs.” In Proc. of Design, Automation and Test in Europe Conference (DATE), 2024.

• [ICCAD] Jiawei Liu, Jianwang Zhai, Mingyu Zhao, Zhe Lin, Bei Yu, Chuan Shi. “PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network.” In Proc. of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2024.

• [FPGA] Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang. “GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network.” In Prof. of ACM/SIGDA 32nd International Symposium on Field-Programmable Gate Arrays (FPGA), 2024.

• [EuroSys] Yijia Zhang, Qiang Wang, Zhe Lin, Pengxiang Xu, Bingqiang Wang. “Improving GPU Energy Efficiency through an Application-transparent Frequency Scaling Policy with Performance Assurance.” In Proc. of The 19th European Conference on Computer Systems (EuroSys), 2024.

2023 and Before

• [TCAD] Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang. “HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS.” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.

• [TCAD] Zhe Lin, Sharad Sinha, Wei Zhang. “Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System.” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 40, no. 11, pp. 2279-2292, 2021.

• [TCAD] Zhe Lin, Sharad Sinha, Wei Zhang. “An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power.” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 9, pp. 1661-1674, 2019.

• [TMSCS] Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang. “Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.” In IEEE Transactions on Multi-Scale Computing Systems (TMSCS), vol. 4, no. 2, pp. 152-162, 2018.

• [DATE] Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian. “PowerGear: Early-stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs.” In Proc. of IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1341-1346, 2022. Best Paper Award Nomination

• [FCCM] Zhe Lin, Sharad Sinha, Wei Zhang. “Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA.” In Proc. of IEEE Field-Programmable Custom Computing Machines (FCCM), pp. 172-180, 2019. Best Paper Award Nomination

• [ASP-DAC] Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang. “HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis.” In Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 574-580, 2020.

• [FPL] Zhe Lin, Wei Zhang, Sharad Sinha. “Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA.” In Proc. of IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 1-8, 2017.

• [KDD] Xunqiang Jiang, Tianrui Jia, Yuan Fang, Chuan Shi, Zhe Lin, Hui Wang. “Pre-training on Large-Scale Heterogeneous Graph.” In Proc. of the 27th ACM SIGKDD Conference on Knowledge Discovery & Data Mining (KDD), 2021.